In ultra large-scale integrated (ULSI) circuit's manufacturing, semiconductor devices are fabricated on a substrate or a silicon wafer. After the formation of the devices, metal lines for interconnection are defined by using a metallic process. As the integration of integrated circuits increases, the manufacturing with high yield and high reliability of metal interconnect lines is hard to achieve. A method to fabricate a metal-damascene structure is to etch trenches for metal interconnect lines and then metal material is refilled into the trenches. The method offers a better way to fabricate the submicron VLSI interconnection with high performance and high reliability, and it becomes be a better structure for metal interconnect of submicron VLSI integrated circuits.
Self-aligned metal-damascene process, where a SiN layer that used as the stopper of a metal-trench etching is sandwiched between two IMD layers, is one of the popular scheme to fabricate the metal-damascene trench structure. In the following description, a conventional method for fabricating a dual damascene structure on a substrate is explained with referring to FIG. 1 to 5.
Referring to FIG. 1, a substrate 100 is provided and a metal interconnect line 10 is fabricated in the substrate 100. An intermetal dielectric (IMD) layer 110 covers the substrate 100 and a silicon nitride layer 120 is formed on the IMD layer 110. As skilled in the art, the IMD layer 110 has a thickness between about 6000 to 10000 angstroms and the silicon nitride layer 120 has a thickness between about 1000 to 2000 angstroms.
Referring to FIG. 2, a lithography and an etching process are performed to form a via pattern. The silicon nitride layer 120 is etched to define an opening in the IMD layer 110 on the metal interconnect line 10. The technology to define the opening on the IMD layer 110 is typically an anisotropically etching process, such as a plasma etching process.
Referring to FIG. 3, an IMD layer 130 is deposited over the silicon nitride layer 120 and it is refilled into the opening. As known in the art, the IMD layer 110 and 130 are typically formed of silicon oxide material, which is deposited by using a conventional chemical vapor deposition (CVD) process.
Referring to FIG. 4, a lithography process and an etching process are performed to form a via hole A, a metal trench C and a metal trench B. The IMD layer 130 and 110 are etched to form the via hole A of the metal interconnect line 10, the metal trench B on the silicon nitride layer 120 and the metal trench C. During the etching of the IMD layer 130 and 110, the silicon nitride layer 120 is used to be an etching stopper to control the depths of the metal trench A and B.
Referring to FIG. 5, a glue/barrier layer 135 is deposited on the sidewalls and the bottom of the via hole A, the trench B and the trench C. Afterwards, a metal layer 140 is refilled into the via hole A, the metal trench B and the metal trench C, and it is deposited on the IMD layer 130. Finally, a chemical mechanical polishing (CMP) process is performed for planarization to remove the metal layer 140 on the IMD layer 130.
However, the major issue concerning the above damascene scheme is the SiN loss. The IMD layer 130 on the silicon nitride layer 120 is etched before the formation of the metal trench C and the silicon nitride layer 120 is simultaneously etched. The silicon nitride layer 120 is used to be an etching stopper of the metal trench B. Thus, a thick SiN layer must be used to control the depth of metal trenches. Nevertheless, because of the thicker silicon nitride layer 120, an additional stress between the thick SiN layer and the IMD layers is induced, and a parasitic capacitance between metal lines is increased.